This invention relates to military anti-jam communications systems, frequency hopping communications systems, and more specifically to frequency hopping synchronizing systems and correlators.
High performance anti-jam military radios such as Link-16, also referred to as JTIDS (Joint Tactical Information Distribution System), have multiple users communicating in a time-division multiple access structure employing direct sequence and frequency hopping anti-jam techniques. These radios have the requirement to acquire timing synchronization for each message. In Link-16, this is accomplished via a burst of 32 synchronization pulses in a synchronization preamble preceding message data pulses. The content of each synchronization pulse is a cryptographically derived code word for a particular time slot and sync pulse. A receiver knows the sync pattern a-priori and configures a correlator to search for the pattern and to correlate. The 32 synchronization pulses are equally spread out over a group of eight frequencies of the 51 frequencies used for frequency hopping in the L-band frequency range. The same eight frequencies are not always used and change in a predetermined manner. With 32 synchronization pulses and eight frequencies, four pulses randomly occur at the same frequency as do all other frequencies in the group of eight frequencies. Typical Link-16 systems correlate on 8 or 16 of the 32 sync pulses and must do so uniquely for each antenna, resulting in 16 to 32 pulse correlation processes running in parallel.
First generation Link-16 products implement the correlation processes with 16 or 32 separate pulse correlators resulting in a very high gate count solution. Second generation Link-16 products use time-shared pulse correlators running at a higher clock frequency than the separate correlator implementation to reduce the overall gate count. This second-generation approach allows each correlator hardware block to perform up to four correlation processes. The number of pulse correlators that can be time-shared in a single hardware block is limited by the maximum clock frequency of the design. As device speeds increase with improvements in technology, the multiplexing architecture used to switch the reference and data inputs to the shared correlator block becomes critical in terms of both speed and size. The existing second-generation approach is still inefficient in both areas and also scales very poorly to higher levels of parallelism.
What is needed is a correlator architecture that can be efficiently implemented in terms of both gate count (size) and maximum clock frequency (speed) and also scales well to higher levels of parallelism.
An enhanced architecture time-shared data correlator for performing a predetermined number of correlation processes is disclosed. The data correlator comprises a data shift register with a predetermined number of input lines for receiving a predetermined number of input data code words of length N at an input data rate R and loading the input data code words at a multiple of the input data rate. The data correlator further comprises a reference shift register for receiving a predetermined number of reference data code words of length N and loading the reference data code words at the multiple of the input data rate. A pulse correlator of length N is connected to the data shift register and the reference shift register for correlating each of the predetermined number of input data code word with its corresponding reference data code word at the multiple of the input data rate to provide a predetermined number of correlation outputs. An accumulator is connected to the pulse correlator for receiving and adding the predetermined number of correlation outputs in accordance with a load/add control signal at a multiple of the input data rate to provide a correlator output. The enhanced architecture time-shared data correlator of claim 1 wherein the predetermined number of correlation processes equals the predetermined number of input data code words. In the enhanced architecture time-shared data correlator, the predetermined number of correlation processes equals the multiple of the input data rate and the predetermined number of reference data code words. In the enhanced architecture time-shared data correlator the data shift register may be a shift register of length 2(N+1)R. The reference shift register comprises N individual shift registers of a length equal to the predetermined number of correlation processes.
It is an object of the present invention to provide an enhanced time-shared data correlator architecture for use in high performance Link-16 synchronization applications.
It is an advantage of the present invention to provide an enhanced time-shared data correlator architecture that reduces gate count and increases clock rate.